A semiconductor element having an insulated gate is used for constituting a power semiconductor device. The power semiconductor device is required to have lower on-resistance in order to save power. For reducing the on-resistance thereof, it is advantageous to make a distance narrower between the periodically arranged semiconductor elements (i.e. unit cells), and thereby to increase the density of channels.
The planar gate and the trench gate are known as the insulated gate structures. A semiconductor device having the trench gate structure may be formed with the narrower distance between the unit cells than a semiconductor device having the planar gate structure, and may increase the channel density. Thus, the trench gate structure is often used for the power semiconductor device to reduce the on-resistance.
As progressing miniaturization of the device size, a mask alignment becomes more difficult in an n-channel transistor, for example, in a process of selectively forming an n+-type source layer on a p-type base layer. Thus, a trench contact structure is used for manufacturing the n-channel transistor, since it is possible to eliminate the mask alignment in the process of forming the n+-type source layer. The trench contact structure is used in a portion, where a source electrode contacts the n+-type source layer and the p-type base layer. The source electrode is embedded in a contact trench extending through the n+-type source layer to the p-type base layer, and electrically connected to the n+-type source layer and the p-type base layer.
Furthermore, a p+-type contact layer is provided in the bottom of the contact trench so that the source electrode is electrically connected to the p-type base layer therethrough, and thereby, a resistance of hole ejection from the p-type base layer to the source electrode is reduced. However, a mask alignment of forming the contact trench may cause variation in a distance between the gate trench and the p+-type contact layer. As the p+-type contact layer comes closer to the gate, the gate threshold voltage for forming inversion channel becomes higher. As a result, the on-resistance may increase depending on accuracy of the mask alignment.